Semiconductor device including stacked semiconductor chips

ABSTRACT

A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of U.S. application Ser. No.12/759,198, filed on Apr. 13, 2010, which is a Continuation of U.S.application Ser. No. 11/418,094, filed on May 5, 2006, now U.S. Pat. No.7,745,919, claiming priority of Japanese Patent Application No.2005-136659, filed on May 9, 2005, the entire contents of each of whichare hereby incorporated by reference.

BACKGROUND OF THE INVENTION

This invention relates to a semiconductor device comprisingsemiconductor chips stacked and, particularly, to a chip selection ordesignation technique.

Various techniques for chip selection or designation in multi-chipsemiconductor device are known using a plurality of through-lines thatare pierced through multiple chips. For example, known techniques aredisclosed in U.S. Pat. No. 6,448,661 and U.S. Pat. No. 6,649,428, whichare incorporated herein by reference in their entireties.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a new arrangement ofa plurality of through-lines in a semiconductor device.

According to one aspect of the present invention, a semiconductor devicecomprises a plurality of semiconductor chips and a predetermined numberof through-lines. Each of the through-lines constitutes an electricalpath shared by the plurality of the semiconductor chips. Thesemiconductor chips are stacked along a predetermined direction. Thethrough-lines are arranged in accordance with a predeterminedconfiguration and are pierced through the semiconductor chips. Thepredetermined configuration is represented by a predetermined simpledirected cycle in a plane perpendicular to the predetermined direction.The predetermined simple directed cycle consists of the predeterminednumber of nodes and the predetermined number of directed edges each ofwhich connects two nodes among the predetermined number of the nodes.

An appreciation of the objectives of the present invention and a morecomplete understanding of its structure may be had by studying thefollowing description of the preferred embodiment and by referring tothe accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view schematically showing a structure of a semiconductordevice in accordance with a first embodiment of the present invention;

FIG. 2 is a table for use in describing an example of a chip selectionor designation method;

FIG. 3 is a table for use in describing another example of a chipselection or designation method;

FIG. 4 is a view schematically showing a structure of an interface chipincluded in the semiconductor device of FIG. 1;

FIG. 5 is a table showing an assertion rule which is used in athrough-line assertion circuit included in the interface chip of FIG. 4;

FIG. 6 is a view schematically showing an example of the through-lineassertion circuit of FIG. 4;

FIG. 7 is a view schematically showing another example of thethrough-line assertion circuit of FIG. 4;

FIG. 8 is a view schematically showing through-lines in accordance withthe first embodiment;

FIG. 9 is a view schematically showing a structure of a semiconductorchip of the first embodiment;

FIG. 10 is a view showing various types of simple directed cycle graphs;

FIG. 11 is a transparent view showing a part of a semiconductor chipaccording to a second embodiment of the present invention;

FIG. 12 is a transparent view showing another part of the semiconductorchip of FIG. 11;

FIG. 13 is a transparent view showing a part of a semiconductor deviceof the second embodiment, wherein the semiconductor chips of FIG. 11 arestacked;

FIG. 14 is a view schematically showing through-lines in accordance withthe second embodiment;

FIG. 15 is a view schematically showing a structure of a semiconductorchip of the second embodiment;

FIG. 16 is a view schematically showing another structure of asemiconductor chip of the second embodiment;

FIG. 17 is a view schematically showing an identification generationcircuit included in the semiconductor chip of a third embodiment;

FIG. 18 is a view schematically showing a signal generation circuitconnected to the identification generation circuit of FIG. 17;

FIG. 19 is a time chart showing an operation of the signal generationcircuit of FIG. 18; and

FIG. 20 is a view showing another identification generation circuit inaccordance with a combination of the first and the third embodiments.

While the invention is susceptible to various modifications andalternative forms, specific embodiments thereof are shown by way ofexample in the drawings and will herein be described in detail. Itshould be understood, however, that the drawings and detaileddescription thereto are not intended to limit the invention to theparticular form disclosed, but on the contrary, the intention is tocover all modifications, equivalents and alternatives falling within thespirit and scope of the present invention as defined by the appendedclaims.

DESCRIPTION OF PREFERRED EMBODIMENTS

A semiconductor device according to a first embodiment of the presentinvention is a dynamic random access memory (DRAM) device and comprisesa plurality of DRAM chips 10-80 as a plurality of semiconductor chipsand an interface chip 100, as shown in FIG. 1. However, the presentinvention is not limited to the DRAM device but may be anothersemiconductor device comprising a plurality of semiconductor chips otherthan DRAM chips.

In the illustrated DRAM device, eight DRAM chips 10-80 are stacked onthe interface chip 100. The DRAM device is provided with a plurality ofthrough-lines each of which is pierced through the DRAM chips 10-80 sothat each through-line constitutes an electrical path shared by the DRAMchips 10-80; the through-lines are used for selecting, designating oridentifying each DRAM chips 10-80.

The through-lines are grouped into a plurality of through-line groups.Each through-line group consists of through-lines whose number is uniqueto the through-line group. The numbers of the through-lines belonging tothe through-line groups are mutually “coprime” to each other. The term“coprime” is used in mathematical meaning and is equal to “relativelyprime”; for example, two integers x and y are coprime or relativelyprime if their greatest common divisor is 1. Likewise, if the greatestcommon divisor of integers x, y and z is 1, the integers x, y and z arecoprime.

To be noted here that the number of possible combinations of coprimenumbers is larger than the total number of the coprime numbers. Based onthe relation in number, a larger number of semiconductor chips aredistinguished designated by using a smaller number of through-lines, inaccordance with the present embodiment. For example, seven through-linesare grouped into two through-line groups; one through-line groupconsists of four through-lines X1-X4, while the other consists of threethrough-lines Y1-Y3. If one through-line is selected for eachthrough-line group and is asserted, the number of possible combinationsof the asserted through-lines becomes twelve. Thus, the grouping ofseven through-lines into four through-lines and three through-linesprovides distinguishablity of twelve semiconductor chips, as shown inFIG. 2. Furthermore, if nine through-lines are grouped into two groups,four through-lines X1-X4 and five through-lines Y1-Y5, twentysemiconductor chips become designatable by selecting and asserting onethrough-line for each through-line groups, as shown in FIG. 3. Likewise,if ten through-lines are grouped into three groups, 2, 3 and 5through-lines, respectively, thirty semiconductor chips (30=2×3×5)become distinguishable.

In this embodiment, there are seven through-lines in total, and they aregrouped into two through-line groups, through-lines X1-4 andthrough-lines Y1-Y3. On the other hand, as mentioned above, there areeight DRAM chips 10-80. In this embodiment, three bank addresses BA0,BA1, BA2 are used for selection/designation of one DRAM chip among theDRAM chips 10-80. In other words, the bank addresses serve asdesignation signals for designation of DRAM chips in this embodiment.

With reference to FIG. 4, the interface chip 100 comprises athrough-line assertion circuit 110 operable in accordance with a truthtable of FIG. 5; the truth table defines the relation between the bankaddresses BA0-BA2 and the asserted through-lines X1-X4 and Y1-Y3. Thethrough-line assertion circuit 110 is adapted to select a combination ofa through-line X1, X2, X3 or X4 and another through-line Y1, Y2 or Y3 onthe basis of the bank addresses BA0-BA2, and to assert the selectedcombination. As understood from FIG. 2, there is a possibility ofdesignation of twelve DRAM chips at maximum. Therefore, if there is afurther bank address BA3 and if the bank address BA3 is also used fordesignation of DRAM chips, twelve DRAM chips can be distinguished byusing seven through-lines X1-X4 and Y1-Y3. In other words, the inputnumber and/or the output number as to the through-line assertion circuit110 are not limited to the present embodiment.

With reference to FIG. 6, there is shown an example of the through-lineassertion circuit 110 a, which comprises a MOD3 circuit and a MOD4circuit and a plurality of primitive elements or gates. The illustratedthrough-line assertion circuit 110 a has an ability of twelve chipdesignation if the further bank address BA3 is delivered to the MOD3circuit and the MOD4 circuit.

With reference to FIG. 7, there is shown another example of thethrough-line assertion circuit 110 b, which consists of a smaller numberof primitive gates. The illustrated through-line assertion circuit 110 bis able to designate only eight chips.

With reference to FIGS. 8 and 9, the DRAM chips 10-80 have terminalsarranged in accordance with the same configuration; in FIGS. 8 and 9,each terminal is depicted with 4A, 4B, 4C or 4D and its subscript of alayer number of the DRAM chip to which the terminal belongs. As apparentfrom FIGS. 8 and 9, the terminals 4A₁-4A₈, 4B₁-4B₈, 4C₁-4C₈, and 4D₁-4D₈are arranged in accordance with a rectangular configuration in each DRAMchip 10-80, and each of the through-lines X1-X4 extends in a straightform. Similarly, other terminals associated with the other group of thethrough-lines Y1-Y3 are arranged in accordance with a triangularconfiguration in each DRAM chip 10-80, and each of the through-linesY1-Y3 extends in a straight form.

Because the through-lines have the straight forms, the assertedterminals corresponding to each DRAM chip 10-80 are different from thoseof the other DRAM chips, as shown in FIG. 9. Therefore, each of the DRAMchip 10-80 has an internal signal generation circuit 11, 21, 31 which isadapted to generate an internal signal 11 a, 21 a, 31 a on the basis ofthe unique combination of the asserted terminals for each DRAM chip,wherein the internal signal 11 a, 21 a, 31 a is indicative of selectionof the DRAM chip where the internal signal generation circuit 11, 21, isprovided. In other words, the DRAM chips 10-80 require layer-specificinternal signal generation circuits so that the DRAM chips 10-80 havedifferent structures than each other. For example, the internal signalgeneration circuit 11 provided for the DRAM chip 10 is connected to theterminals 4A₁ and 3A₁; the internal signal generation circuit 21provided for the DRAM chip 20 is connected to the terminals 4A₂ and 3A₂;and the internal generation circuit 31 provided for the DRAM chip 30 isconnected to the terminals 4A₃ and 3A₃.

A DRAM device according to a second embodiment of the present inventionis a modification of the DRAM device of the first embodiment. The DRAMdevice of the second embodiment comprises an interface chip and aplurality of DRAM chips, wherein the interface chip is the same one asthat of the first embodiment, while the DRAM chips are different fromthose of the first embodiment and have the same structure as each other,as described in detail below.

In the following description, the terminology in graph theory is used;the words are briefly explained here. A cycle is a word used in graphtheory and is a closed path whose start node and end node are the same.A directed cycle consists of nodes and directed edges or arcs. In otherwords, a directed cycle includes no undirected edges; all nodes includedin the simple directed cycle are ordered. A simple directed cycle is adirected cycle with no repeated nodes. In other words, the number ofnodes is equal to the number of directed edges in a simple directedcycle.

Various simple directed cycles are illustrated in FIG. 10. The first onehas two nodes 2A and 2B. The second one has three nodes 3A-3C. Intheory, the third one is also a simple directed cycle in which the nodes5A, 5E, 5B, 5D, 5C are repeatedly ordered in this order. Furthermore,the fourth one is a simple directed cycle, too, wherein the nodes 5A-5Care physically arranged on a common straight line.

With reference to FIG. 11, each of the DRAM chips comprises componentsconstituting the through-lines X1-X4. In detail, each DRAM chip haslower and upper surfaces and comprises four lower terminals 4A-4D, fourupper terminals 4A′-4D′ and four connection portions. The lowerterminals 4A-4D are formed on the lower surface of the DRAM chip. On theother hand, the upper terminals 4A′-4D′ are formed on the upper surfaceof the DRAM chip. The lower terminals 4A-4D are arranged incorrespondence with the upper terminals 4A′-4D′, respectively. In otherwords, the upper terminals 4A′-4D′ are arranged above the lowerterminals 4A-4D, respectively. However, the upper terminals 4A′, 4B′,4C′, 4D′ are not connected to the lower terminals 4A, 4B, 4C, 4D,respectively, but are connected by the connection portions 4B″, 4C″,4D″, 4A″ to the lower terminals 4B, 4C, 4D, 4A, respectively, as shownin FIG. 11. In other words, there is a simple directed cycle whichcirculates according to the order “4D-4C-4B-4A-4D”, and each of theconnection portions 4B″, 4C″, 4D″, 4A″ connects one of the lowerterminals 4B, 4C, 4D, 4A and one of the upper terminals 4A′, 4B′, 4C′,4D′ in accordance with one of the directed edges 150. The first directededge 151 corresponding to the connection portion 4B″ has start and endnodes which correspond to the lower terminal 4B and the upper terminal4A′, respectively. The second directed edge 152 corresponding to theconnection portion 4C″ has start and end nodes which correspond to thelower terminal 4C and the upper terminal 4B′, respectively. The directededge corresponding to the connection portion 4D″ has start and end nodeswhich correspond to the lower terminal 4D and the upper terminal 4C′,respectively. The directed edge corresponding to the connection portion4A″ has start and end nodes which correspond to the lower terminal 4Aand the upper terminal 4D′, respectively.

Likewise, each of the DRAM chips further comprises componentsconstituting the through-lines Y1-Y3, as shown in FIG. 12. In detail,each DRAM chip further comprises three lower terminals 3A-3C, threeupper terminals 3A′-30′ and three connection portions 3A″-30″. The lowerterminals 3A-3C are formed on the lower surface of the DRAM chip. On theother hand, the upper terminals 3A′-3C′ are formed on the upper surfaceof the DRAM chip. The lower terminals 3A-3C are arranged incorrespondence with the upper terminals 3A′-3C′, respectively. The upperterminals 3A′, 3B′, 3C′ are connected by the connection portions 3B″,3C″, 3A″ to the lower terminals 3B, 3C, 3A, respectively, as shown inFIG. 12. In other words, there is a simple directed cycle whichcirculates according to the order “3C-3B-3A-3C”, and each of theconnection portions 3B″, 3C″, 3A″ connects one of the lower terminals3B, 3C, 3A and one of the upper terminals 3A′, 3B′, 3C′ in accordancewith one of the directed edges. The directed edge corresponding to theconnection portion 3B″ has start and end nodes which correspond to thelower terminal 3B and the upper terminal 3A′, respectively. The directededge corresponding to the connection portion 3C″ has start and end nodeswhich correspond to the lower terminal 3C and the upper terminal 3B′,respectively. The directed edge corresponding to the connection portion3A″ has start and end nodes which correspond to the lower terminal 3Aand the upper terminal 3C′, respectively.

As shown in FIG. 13, the DRAM chips with the above-mentioned structuresare stacked so that the through-lines X1-X4 as well as the through linesY1-Y3 are formed as shown in FIG. 14. In detail, the DRAM chip 20 isstacked on the DRAM chip 10 so that the lower terminals 4A₂-4D₂ of theDRAM chip 20 are mounted and connected to the upper terminals 4A′₁-4D′₁of the DRAM chip 10; the lower terminals 4A₃-4D₃ of the DRAM chip 30 areconnected to the upper terminals 4A′₂-4D′₂ of the DRAM chip 20; thelower terminals 4A₄-4D₄ of the DRAM chip 40 are connected to the upperterminals 4A′₃-4D′₃ of the DRAM chip 30. Thus, the through-lines X1-X4are formed by the lower terminals 4A_(n)-4D_(n), the upper terminals4A′_(n)-4D′_(n) and the connection portions 4A″_(n)-4D″_(n). The otherthrough-lines Y1-Y3 are also formed simultaneously upon the stacking theDRAM chips.

Thus obtained through-lines X1-X4 have helix forms, respectively, asshown in FIG. 14. Especially, each of the helix form is a polygonalhelix. In detail, a polygon is a closed planar path composed of a finitenumber of sequential line segments. The straight line segments that makeup the polygon are called its sides or edges and the points where thesides meet are the polygon's vertices. A simple polygon is a polygonthat has a single, non-intersecting boundary. A polygonal helix is ahelix that has a polygon form as seen along its helical axis.

With reference to FIG. 15, the DRAM chips 10, 20, 30 have the samestructure as each other. In detail, the DRAM chips 10, 20, 30 have thesame structured internal signal generation circuits 12, 22, 32 adaptedto generate an internal signals 12 a, 22 a, 32 a, respectively.

To be noted here that in this embodiment, each of the through-linesX1-X4, Y1-Y3 does not have a straight form and passes through theterminals corresponding to the different positions on the DRAM chips,respectively, as shown in FIGS. 14 and 15. For example, the through-lineX1 passes through the terminal 4A₁ of the DRAM chip 10, the terminal 4D₂of the DRAM chip 20 and the terminal 4C₃ of the DRAM chip 30; thethrough-line X2 passes through the terminal 4B₁ of the DRAM chip 10, theterminal 4A₂ of the DRAM chip 20 and the terminal 4D₃ of the DRAM chip30; the through-line X3 passes through the terminal 4C₁ of the DRAM chip10, the terminal 4B₂ of the DRAM chip 20 and the terminal 4A₃ of theDRAM chip 30; and the through-line X4 passes through the terminal 4D₁ ofthe DRAM chip 10, the terminal 4C₂ of the DRAM chip 20 and the terminal4B₃ of the DRAM chip 30. Likewise, the through-line Y1 passes throughthe terminal 3A₁ of the DRAM chip 10, the terminal 3C₂ of the DRAM chip20 and the terminal 3B₃ of the DRAM chip 30; the through-line Y2 passesthrough the terminal 3B₁ of the DRAM chip 10, the terminal 3A₂ of theDRAM chip 20 and the terminal 3C₃ of the DRAM chip 30; and thethrough-line Y3 passes through the terminal 3C₁ of the DRAM chip 10, theterminal 3B₂ of the DRAM chip 20 and the terminal 3A₃ of the DRAM chip30.

With reference to FIGS. 5, 14 and 15, each of the DRAM chips isdesignated or selected when the combination of the terminals 4A_(n) andthe terminal 3A_(n) is asserted, where n is integer of 1 to 8 andcorresponds to a layer number of the DRAM chip 10-80. The terminals4A_(n) and the terminal 3A_(n) are referred to as specific terminals.The specific terminals 4A_(n) and 3A_(n) are positioned at particularvertices on the rectangle configuration and the triangle configuration,respectively. On each DRAM chip 10, 20, 30, the internal signalgeneration circuit 12, 22, 32 is coupled to the specific terminals4A_(n) and 3A_(n) and is adapted to generate the internal signal 12 a,22 a, 32 a based on the specific terminals 4A_(n) and 3A_(n). In thisembodiment, the internal signal generation circuits 12, 22, 32 are alsoconnected to the terminals 4B_(n)-4D_(n) and the terminals 3B_(n) and3C_(n) in the same manner for every DRAM chip. The thus-structuredinternal signal generation circuit 12, 22, 32 does not generate theinternal signal 12 a, 22 a, 32 a when the terminal 4B_(n)-4D_(n) or theterminal 3B_(n), 3C_(n) is asserted even if the specific terminals4A_(n) and 3A_(n) is asserted. Thus, the internal signal generationcircuits 12, 22, 32 can prevent incorrect actions and havehigh-reliability.

The internal signal generation circuits 13, 23, 33 can be simplified asshown in FIG. 16, wherein each of the internal signal generationcircuits 13, 23, 33 is connected only to the specific terminals 4A_(n)and 3A_(n) and is adapted to generate the internal signal only on thebasis of the monitoring results of the specific terminals 4A_(n) and3A_(n).

A DRAM device according to a third embodiment of the present inventioncomprises a different interface chip which a through-line assertioncircuit is not provided for and, when the DRAM device is used, one ofthe through-lines X1-X4 and one of the through-lines Y1-Y3 are fixedlyasserted. In this embodiment, only the through-line X1 and thethrough-line Y1 are fixedly asserted, for example, by supplying thethrough-line X1 and the through-line Y1 with VDD, while by supplying thethrough-line X2-X4 and the through-line Y2, Y3 with GND. In this case,because the combination of the asserted terminals is unique to each DRAMchips, the DRAM chip can acknowledge its layer number by checking thecombination of the asserted terminals.

With reference to FIG. 17, an identification generation circuit 105 isprovided for each DRAM chip. The identification generation circuit 105is connected to the terminals 4A-4D and the terminals 3A-3C. Theidentification generation circuit 105 is adapted to generate anidentification signal ID1-ID8 on the basis of the combination of theasserted terminals 4A-4D, 3A-3C, wherein the identification signalID1-ID8 is indicative of the layer number of the DRAM chip.

With reference to FIG. 18, a signal generation circuit 106 comprises ap-ch transistor 106 b, two-inputs NAND circuits 106 c, eight in number,and a latch circuit 106 d. The p-ch transistor 106 b is connectedbetween the power supply and the point 106 a and is used forpre-charging the point 106 a in response to a pre-charge signal α. Thepre-charge signal α is changed into low state when the point 106 a is tobe pre-charged. Each of the NAND circuits 106 c is connected between thepoint 106 a and the ground (GND). The latch circuit 106 d holds a levelof the point 106 a and transmits the level to an internal signal line106 e.

One of the inputs for each NAND circuits 106 c is a corresponding one ofthe identification signals ID1-ID8; the other is a layer designationsignal indicative of a layer number of the DRAM chip to be designated.The layer designation signal is shown as BA0N1N2N, BA0T1N2N, BA0N1T2N,BA0T1T2N, BA0N1N2T. BA0T1N2T, BA0N1T2T, or BA0T1T2T, where “N” indicates“NOT” (=false:0), while “T” indicates “TRUE” (=1). For example, if onlythe first layer DRAM chip is to be designated, the layer designationsignal BA0N1N2N is asserted, while the other layer designation signalsare negated. Likewise, if only the second layer DRAM chip is to bedesignated, the layer designation signal BA0T1N2N is asserted, while theother layer designation signals are negated. The layer designationsignals are obtained by decoding the encoded designation signals, i.e.the bank signals BA0-BA2 in this embodiment. The decoding may be carriedout by the interface chip or by each DRAM chip.

With further reference to FIG. 19, explanation is made about anoperation of the signal generation circuit 106 which is embedded in thefirst layer DRAM chip 10. The identification generation circuit 105 ofthe DRAM chip 10 generates ID1 of low level and ID2-ID8 of high levels.Before the chip selection/designation, the pre-charge signal α isasserted so that the point 106 a is pre-charged to have the high level.The pre-charged level is held by the latch circuit 106 d and istransmitted to the internal signal line 106 e. Under that state, whenthe first layer DRAM chip 10 is designated with the asserted layerdesignation signal BA0N1N2N, the corresponding NAND circuit 106 c turnsON so that the level of the point 106 a is changed into the low level.The change of the point 106 a is transmitted to the internal signal line106 e. Thus, the illustrated internal signal generation circuit 106asserts the internal signal line 106 e only upon the match between thelayer number of the identification signal and the designated layernumber.

The preferred embodiments described above can be modified in variousmanner. For example, the conceptual combination of the first and thethird embodiments allows the DRAM chips to have the same structure aseach other even if each of the through-lines has a straight form asshown in FIG. 8. FIG. 20 shows an example of another identificationgeneration circuit 105 a which allows the conceptual combination of thefirst and the third embodiments. The DRAM chips can have the samestructure as each other; each of the DRAM chips comprises theidentification generation circuit 105 a shown in FIG. 20 and internalsignal generation circuit 106 shown in FIG. 18. In the preferredembodiments, the through-lines are grouped into two or more groups butmay form only a single group. In the preferred embodiments, the bankaddresses are used as designation signals, but other signals including achip-select signal may be used. In the preferred embodiment, only oneDRAM chip is designated, but two or more DRAM chips can be designatedsimultaneously, as apparent from their structures.

While there has been described what is believed to be the preferredembodiment of the invention, those skilled in the art will recognizethat other and further modifications may be made thereto withoutdeparting from the spirit of the invention, and it is intended to claimall such embodiments that fall within the true scope of the invention.

1-17. (canceled)
 18. A method comprising: forming a plurality ofsemiconductor chips, each of the semiconductor chips including: lowerand upper surfaces; a plurality of lower terminals on the lower surface;a plurality of upper terminals on the upper surface, each of the upperterminals being vertically aligned correspondingly with one of the lowerterminals; and a plurality of conductive lines, each of the conductivelines being provided to electrically connect an associated one of thelower terminals to an associated one of the upper terminals which is notvertically aligned with the associated one of the lower terminals; andstacking the plurality of semiconductor chips with each other such thatthe upper terminals of a lower one of the semiconductor chips arerespectively connected to the lower terminals of an upper one of thesemiconductor chips and that each of the lower terminals of thelowermost one of the semiconductor chips are connected through theconductive lines to, and vertically aligned with, a corresponding one ofthe upper terminals of an uppermost one of the semiconductor chips. 19.The method as claimed in claim 18, wherein the conductive linesrespectively extend from the lower terminals to the upper terminals indifferent vectors from each other in a plan view.
 20. The method asclaimed in claim 18, wherein the upper electrodes of each of thesemiconductor chips are arranged at vertices of a polygon.
 21. Themethods as claimed in claim 20, wherein the lower electrodes of each ofthe semiconductor chips are arranged at vertices of a polygon.
 22. Amethod comprising: forming a plurality of semiconductor chips eachincluding lower and upper surfaces, the forming the semiconductor chipscomprising: providing a plurality of lower terminals on the lowersurface apart from each other, the lower terminals including a firstlower terminal, providing a plurality of upper terminals on the uppersurface apart from each other, the upper terminals including a firstupper terminal that is vertically aligned with the first lower terminal,and providing a plurality of conductive lines to electrically connect anassociated one of the lower terminals including the first lower terminalto an associated one of the upper terminals including the first upperterminal, the associated ones of the lower and upper terminals to beelectrically connected to each other through an associated one of theconductive lines being not aligned with each other; and stacking theplurality of semiconductor chips with each other such that the upperterminals of a lower one of the semiconductor chips are connectedrespectively to the lower terminals of an upper one of the semiconductorchips and that the first lower terminal of an lowermost one of thesemiconductor chips is vertically aligned with, and electricallyconnected to, the first, upper terminal of an uppermost one of thesemiconductor chips through one or ones of the semiconductor chipsbetween the lowermost and uppermost semiconductor chips.
 23. The methodas claimed in claim 22, wherein the lower terminals including the firstlower terminal are provided to be arranged at vertices of a polygon. 24.The method as claimed in claim 23, wherein the upper terminals includingthe first upper terminal are provided to be arranged at vertices of apolygon.
 25. A method comprising: forming at least first, second andthird semiconductor chips each including a semiconductor body havinglower and upper surfaces, the forming the first, second and thirdsemiconductor chips comprising: providing at least first, second andthird lower terminals on a side of the lower surface, providing at leastfirst, second and third terminals on a side of the upper surface, thefirst, second and third upper terminals being vertically alignedrespectively with the first, second and third lower terminals, andproviding at least first, second and third conductive lines eachincluding a connection portion penetrating trough the semiconductorbody, each of the first, second third conductive lines electricallyconnecting an associated one of the first, second and third lowerelectrodes to an associated one of the first, second and third upperterminals which is not vertically aligned with the associated one of thelower terminals; and stacking the first, second and third semiconductorchips with each other such that the first, second and third upperterminals of a lower one of the first, second and third semiconductorchips are connected respectively to the first, second and third lowerterminals of an upper one of the first, second and third semiconductorchips and that each of the first, second and third lower terminals of alowermost one of the first, second and third semiconductor chips iselectrically connected to a corresponding one of the first, second andthird upper terminals of an uppermost one of the first, second and thirdsemiconductor chips which are vertically aligned respectively with thefirst, second and third lower electrodes of the lowermost one of thefirst, second and third semiconductor chips.
 26. The method as claimedin claim 25, wherein the providing the first, second and thirdconductive lines is carried out such that each of the first, second andthird conductive lines further includes an interconnection line providedbetween the connection portion and an associated one of the first,second and third upper terminals to electrically connect the associatedone of the first, seconds and third lower terminals to the associatedone of the first, second and third upper terminals which is notvertically aligned with the associated one of the first, second andthird lower terminals.
 27. The method as claimed in claim 25, whereinthe providing the first, second and third upper terminals is carried outsuch that the first, second and third upper terminals are arranged atvertices of a polygon.
 28. The method as claimed in claim 25, whereinthe providing the first, second and third conductive lines is carriedout such that the connection portions of the first, second and thirdconductive lines are vertically aligned with the first, second and thirdlower electrodes and with the first, second and third upper terminalsand that the connection portions of the first, second and thirdconductive lines are connected, respectively with the first, second andthird lower terminals.
 29. The method as claimed in claim 28, whereinthe providing the first, second and third conductive lines is carriedout such that each of the first, second and third conductive linesfurther includes an interconnection line provided between the connectionportion and an associated one of the first, second and third upperterminals to electrically connect the associated one of the first,seconds and third lower terminals to the associated one of the first,second and third upper terminals which is not vertically aligned withthe associated one of the first, second and third lower terminals. 30.The method as claimed in claim 29, wherein the providing the first,second and third upper terminals is carried out such that the first,second and third upper terminals are arranged at vertices of a polygon.31. The method as claimed in claim 30, wherein the providing the first,second and third lower terminals is carried out such that the first,second and third lower terminals are arranged at vertices of a polygon.